2019134 - UVM Verification Engineer
This is for our client in Sweden, looking for someone who can work in Design Verification for any location.
- Minimum 8 + years’
experience of ASIC and/or FPGA verification.
- Block/ System/ Sub-system verification using SV+UVM. 4+ years of experience in UVM.
- Scripting using – Python, TCL, and/or Perl.
Good to have:
- Ethernet knowledge.
- Verification using Specman E.
- CPRI knowledge.
- Correction algorithms and Encryption algorithms.
- Radio Access Technology.
- Formal Verification and Top-Level verification.
- High Level Synthesis.
- Lab measurements on FPGA platforms.
- Experience in mixed signal development.
- ASIC STA analysis.
- Good team player with attention to detail, self-disciplined, able
to manage their own time and workload, proactive and motivated.
sense of responsibility and commitment, innovative thinking.