2020075 - UVM Verification Engineers
You will be working in a team
who builds/verify the products for next generation Cameras. You take ownership
of the verification of platform products like reference design and so.
- Creating and reviewing design verification
documentation/ test plans.
- Designing and implementing verification and
- Creating coverage models.
- Testing and debugging VHDL, Verilog, and SystemVerilog RTL.
- Working alongside the design team to ensure the
quality of the design work done along with on time delivery.
- Integrating various blocks and verify the functional
- Minimum 8 + years’ experience of ASIC and/or FPGA
- Block/ System/ Sub-system verification using SV+UVM.
- 4+ years of experience in UVM.
- Python Scripting.
Good to have:
- Good knowledge of C/C++ Languages is preferable. At least you should be able to correct syntax
and compile the code when needed(rarely).
- Scripting TCL, and/or Perl
- Lab measurements on FPGA platforms.
- Good team player with attention to detail, self-disciplined, able to
manage their own time and workload, proactive and motivated.
- Strong sense of responsibility and commitment, innovative thinking.
- Great communication skills.