2021017 - UVM Verification Engineer
You will, as part of a project team, take ownership of
the verification of particular blocks as well as system level verification within
the product architecture, moving through all phases of the design and
- Creating and reviewing design verification documentation/ test plans.
- Designing and implementing verification IP and test-benches.
- Creating coverage models.
- Testing and debugging VHDL, Verilog, and System Verilog RTL.
- Planning and tracking tasks to meet the targets at the planned time.
- Working alongside the design team to ensure the quality of the design work
done along with on time delivery.
- Creating Assertion based model to ensure protocol checking.
- Integrating various blocks and verify the functional correctness.
- Minimum 8 + years’
experience of ASIC and/or FPGA verification.
- Block/ System/ Sub-system verification using SV+UVM. 4+ years of experience in UVM.
- Scripting using – Python, TCL, and/or Perl.
Good to have:
- Domain competence around BaseBand and 5G but not necessary
- BackEnd Integration Experience
- Knowledge in High speed interfaces like Ethernet, CPRI and switching
- Verification using Specman E.
- Correction algorithms and Encryption algorithms.
- Formal Verification and Top-Level verification.
- High Level Synthesis.
- Lab measurements on FPGA platforms.
- Experience in mixed signal development.
- Good team player with attention to detail, self-disciplined, able
to manage their own time and workload, proactive and motivated.
sense of responsibility and commitment, innovative thinking.