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2021087 - ASIC Design Engineer

8-10 years

Job Description

Our customer is reputable Telecom OEM. The group that you will be working with implementation of radio algorithms (e.g. DPD, CF etc) on chip for production radio base stations. The RTL/VHDL mainly for FPGA but, some also goes ASIC. It’s a 20 people implementation team, including testing HW in lab. Algorithms are development by others. 


Requirements - Must list (short, and real must, no order

  • Minimum 5 + years’ experience of using VHDL
  • Simulation experience using one of ModelSim/QuestaSim/Incisive
  • Fundamental understanding of signal processing
  • RTL for ASIC-targets
  • Experience from System-on-Chip (FPGA with embedded processors)
  • Experience from Xilinx Vivado 2017/2018
  • Excellent written and verbal communication skills in English
  • Bachelor’s degree in Electrical or Computer Engineering or similar

Soft skills
  • Good team player with attention to detail, self-disciplined, able to manage their own time and workload, proactive and motivated
  • Strong sense of responsibility and commitment, innovative thinking

Good to have
  • Multi-Gigabit Transceivers on FPGA
  • VUnit/UVM/(UVVM)
  • Timing closure and design constraining
  • Masters degree in Electrical or Computer Engineering or similar

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